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IS31AP4832 integrated silicon solution, inc. ? www.issi.com 1 rev.a, 12/29/2011 dual 2.5w audio power amplifier and stereo headphone driver with tone control and 3d enhancement january 2012 general description the IS31AP4832 is a monolithic integrated circuit that provides tone (bass and treble) controls as well as a stereo audio power amplifier capable of delivering 2.5w (typ.) into 4 ? or 1.7w (typ.) into 8 ? with less than 10% thd with a 5v supply. the IS31AP4832 uses flexible i 2 c control interface for multiple application requirements. the IS31AP4832 also features 3d sound circuitry which can be externally adjusted via a simple rc network. the headphone amplifier features output capacitor-less (ocl) architecture that eliminates the output coupling capacitors required by traditional headphone amplifiers. the IS31AP4832 features a 13 step tone control for the headphone and stereo outputs. the device mode select and tone are controlled through an i 2 c compatible interface. thermal shutdown protection prevents the device from being damaged during fault conditions. superior click and pop suppression eliminates audible transients on power-up/down and during shutdown. features ? 3d enhancement ? treble and bass control ? i 2 c control interface ? thermal shutdown protection ? minimum external components ? click-and-pop suppression ? micro-power shutdown ? software & hardware control shutdown function ? qfn-28(4mm 4mm) package applications ? cell phones, pda, mp4,pmp ? portable and desktop computers ? desktops audio system ? multimedia monitors typical application circuit left channel 3d enhance right channel 3d enhance left channel tone control right channel tone control - + - + - + - + pouta nouta poutb noutb voc 0.22uf 2.2nf left tone in left tone out 0.1uf vdd 4,18 11,13,25 + - - + + - 20k 0.22uf left input left input right input right input 2.2nf 0.68uf left 3d in right 3d in left loop out 20k 2.2nf 20k 20k i 2 c interface 5k biass click/pop suppresion left loop in i 2 c bus right loop out right tone in right tone out right loop in 1 5 16 78 9 10 12 14 15 21 28 27 22 23 24 3 17 19 sda scl 10uf hp logic phone jack gnd speaker speaker 1f 26 bypass vdd gnd shutdown working lh 6 shutdown gnd vdd on off h l i2c reset 20 2.2nf 30pf 30pf 100k figure 1 typical application circuit
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 2 rev.a, 12/29/2011 pin configuration package pin configuration (top view) qfn-28 1 2 3 4 5 6 28 27 26 25 24 23 gnd gnd pouta vdd nouta poutb vdd noutb left input right input sda scl l3din r3din bypass nc i2c reset voc 7 22 8 9 10 11 12 13 14 21 20 19 18 17 16 15 left loop in left tone in left tone out left loop out right loop in right tone in right tone out right loop out shutdown gnd copyright ? ? ? 2011 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products ? at ? any ? time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c.) ? potential ? liability ? of ? integrated ? silicon ? solution, ? inc ? is ? adequately ? protected ? under ? the ? circumstances
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 3 rev.a, 12/29/2011 pin description no. pin description 1 left input left channel input. 2 nc not connection. 3 pouta left channel +output in btl mode. 4,18 vdd supply voltage. 5 nouta left channel ?output in btl mode. 6 shutdown ??????????? it will be into shutdown mode when pull low. 7 left loop out left channel tone control loop out. 8 left tone in left channel tone control in. 9 sda the input for the i2c data signal. 10 scl the input for the i2c clock signal. 11,13,25 gnd gnd. 12 left loop in left channel tone control loop in. 14 left tone out left channel tone control out. 15 r3din right channel 3d input. 16 l3din left channel 3d input. 17 noutb right channel ?output in btl mode. 19 poutb right channel +output in btl mode. 20 i2c reset reset chip logic and states. internal pulled low to enable communication; pull high to reset IS31AP4832 to power on default mode and stop communication; a longer than 200ns high pulse can reset the chip. 21 right input right channel input. 22 right tone out right channel tone control out. 23 right loop in right channel tone control loop in. 24 voc reference (1/2 v dd ) of headphone. 26 bypass bypass capacitor which provides the common mode voltage. 27 right tone in right channel tone control in. 28 right loop out right channel tone control loop out. thermal pad connect to gnd.
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 4 rev.a, 12/29/2011 ordering information industrial range: -40c to +85c order part no. package qty/reel IS31AP4832-qfls2-tr qfn-28, lead-free 2500
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 5 rev.a, 12/29/2011 absolute maximum ratings supply voltage, v dd - 0.3v ~ +6.0v voltage at any input pin - 0.3v ~ v dd +0.3v maximum junction temperature, t jmax 150c storage temperature range, t stg - 65c ~ +150c operating temperature range, t a ? 40c ~ +85c solder information, vapor phase (60s) infrared (15s) 215c 220c note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the sp ecifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics the following specifications apply for v dd = 5v, unless otherwise noted. limits apply for t a =25c. symbol parameter condition typ. limit unit v dd supply voltage 3.0 v(min) 5.5 v(max) i dd quiescent power supply current v in = 0v, io = 0a, btl mode v in = 0v, io = 0a, se mode 8 5 11 7 ma(max) ma(max) i sd shutdown current standby mode 1.75 5 a(max) t wu turn on time c b p = 1 f 130 ms v oc inside ground for headphone v in = 0 2.5 v v il sd shutdown pin input low voltage 0.4 v(max) v ih sd shutdown pin input high voltage 1.4 v(min) bass control a r attenuator range f = 100hz, v in = 0.25v 12 db as bass step size 2 db e se bass step size error 0.5 db(max) e t bass tracking error 0.15 db(max) treble control a r attenuator range f = 10khz, v in = 0.25v 12 db as treble step size 2 db e se treble step size error 0.1 db(max) e t treble tracking error 0.15 db(max) i 2 c bus timing f max maximum bus frequency 400 khz t start;hold start signal: hold time before clock/data transitions 0.6 s t d ; setu p data setup time 0.1 s t c ; hi g h minimum high clock duration 0.6 s t c ; low minimum low clock duration 1.3 s t stop;setup stop signal: setup time before clock/data transitions 0.6 s i 2 c bus input and output v il i2c i 2 c input low voltage 0.8 v(max) v ih i2c i 2 c input high voltage 1.6 v(min) i in input current 0.15 a vo output voltage?sda acknowledge 0.2 v(max)
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 6 rev.a, 12/29/2011 electrical characteristics for bridged-mode operation (5v) symbol parameter condition typ. limit unit vos output offset voltage v in = 0v 5 25 mv(max) po output power thd+n = 1%, f = 1khz, r l = 4 ? 1.9 w thd+n = 1%, f = 1khz, r l = 8 ? 1.2 1.0 w(min) thd+n = 10%, f = 1khz , r l = 4 ? 2.5 w thd+n = 10%, f = 1khz, r l = 8 ? 1.7 thd+n total harmonic distortion +noise 1khz a vd = 2, r l = 4 ? , po = 0.5w 0.12 % 1khz a vd = 2, r l = 8 ? , po = 0.2w 0.03 psrr power supply rejection ratio input grounded 217hz, v ripple = 200mv p-p c bp = 1 f, r l = 8 ? 70 db input grounded 1khz, v ripple = 200mv p-p c bp = 1 f, r l = 8 ? 64 db x talk channel separation f = 1khz, c bp = 1 f stereo enhanced control = low 88 db v no output noise voltage 1khz, a-weighted 10 v electrical characteristics for single-ended operation (5v) symbol parameter condition typ. limit unit po output power thd+n = 0.5%,f = 1khz, r l = 32 ? 90 85 mw(min) thd+n total harmonic distortion + noise po = 75mw,1khz, r l = 32 ? 0.015 % psrr power supply rejection raito input grounded 217hz, v ripple = 200mv p-p c bp = 1 f, r l = 32 ? 75 db input grounded 1khz, v ripple = 200mv p-p c bp = 1 f, r l = 32 ? 72 db v no output noise voltage 1khz, a-weighted 25 v
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 7 rev.a, 12/29/2011 electrical characteristics for bridged-mode operation (3v) symbol parameter condition typ. limit unit vos output offset voltage v in = 0v 2.5 mv po output power thd+n = 1%, f = 1khz, r l = 4 ? 0.7 w thd+n = 1%, f = 1khz, r l = 8 ? 0.45 thd+n = 10%, f = 1khz, r l = 4 ? 0.88 thd+n = 10%, f = 1khz, r l = 8 ? 0.55 thd+d total harmonic distortion+noise 1khz, a vd = 2, r l = 4 ? , po = 0.35w 0.12 % 1khz, a vd = 2, r l = 8 ? , po = 0.15w 0.08 psrr power supply rejection ratio input grounded 217hz v ripple = 200mv p-p , c bp = 1 f, r l = 8 ? 71 db input grounded 1khz v ripple = 200mv p-p , c bp = 1 f, r l = 8 ? 65 db v no output noise voltage 1khz, a-weighted 10 v electrical characteristics for single-ended operation (3v) symbol parameter condition typ. limit unit po output power thd+n = 0.5%,f = 1khz, r l = 32 ? 32 mw thd+n total harmonic distortion+noise po = 25mw, 1khz, r l = 32 ? 0.02 % v no output noise voltage 1khz, a-weighted 25 v
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 8 rev.a, 12/29/2011 typical performance characteristics 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k hz figure 2 thd+n vs. frequency vdd=3v, rl=4ohm, btl, po=350mw, avd=2, bw=80khz 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k hz figure 4 thd+n vs. frequency vdd=3v, rl=8ohm, btl, po=150mw, avd=2, bw=80khz 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k hz figure 6 thd+n vs. frequency vdd=3v, rl=32ohm, se, po=25mw, avd=2, bw=80khz 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k hz figure 3 thd+n vs. frequency vdd=5v, rl=4ohm, btl, po=500mw, avd=2, bw=80khz 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k hz figure 5 thd+n vs. frequency vdd=5v, rl=8ohm, btl, po=200mw, avd=2, bw=80khz 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k hz figure 7 thd+n vs. frequency vdd=5v, rl=32ohm, se, po=75mw, avd=2, bw=80khz
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 9 rev.a, 12/29/2011 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 % 10m 2 20m 50m 100m 200m 500m 1 w figure 8 thd+n vs. output power vdd=3v, rl=4ohm, btl, avd=2, bw=80khz 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 % 10m 1 20m 50m 100m 200m 500m w figure 10 thd+n vs. output power vdd=3v, rl=8ohm, btl, avd=2, bw=80khz 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 % 1m 80m 2m 3m 5m 7m 20m 40m w figure 12 thd+n vs. output power vdd=3v, rl=32ohm, se, avd=2, bw=80khz 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 % 10m 3 20m 50m 100m 500m 1 2 w figure 9 thd+n vs. output power vdd=5v, rl=4ohm, btl, avd=2, bw=80khz 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 % 10m 2 20m 50m 100m 200m 500m 1 w figure 11 thd+n vs. output power vdd=5v, rl=8ohm, btl, avd=2, bw=80khz 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 % 1m 200m 2m 5m 10m 20m 50m w figure 13 thd+n vs. output power vdd=5v, rl=32ohm, se, avd=2, bw=80khz 1kh z 20hz 20 h z 1kh z 1kh z 20 h z 20 h z 1kh z 20 h z 1kh z 1 0 kh z 1 0 kh z 1 0 kh z 1 0 kh z 1 0 kh z
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 10 rev.a, 12/29/2011 figure 14 psrr vs. frequency vdd=3v, rl=8ohm, btl, input ac-grounded 1u 100u 2u 5u 10u 20u 50u v 20 20k 50 100 200 500 1k 2k 5k hz figure 16 noise floor a-weighted -20 +20 -15 -10 -5 +0 +5 +10 +15 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 18 base response vs. frequency vdd=5v, rl=8ohm, btl figure 15 psrr vs. frequency vdd=5v, rl=8ohm, btl, input ac-grounded -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 17 crosstalk vdd=5v, rl=8ohm, btl -20 +20 -15 -10 -5 +0 +5 +10 +15 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 19 treble response vs. frequency vdd=5v, rl=8ohm, btl 3v and 5v btl, 8ohm 3v and 5v se, 32ohm b to a a to b
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 11 rev.a, 12/29/2011 -20 +20 -15 -10 -5 +0 +5 +10 +15 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 20 bass and treble response vs. frequency vdd=5v, rl=8ohm, btl timing diagrams figure 21 i2c bus format figure 22 i2c timing diagram see electrical characteristics section for timing specifications
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 12 rev.a, 12/29/2011 truth tables software specification chip address msb lsb 1 0 0 0 0 0 0 0 data bytes (brief description) msb lsb function 0 0 1 x d3 d2 d1 d0 bass control 0 1 0 x d3 d2 d1 d0 treble control 1 1 1 x d3 d2 d1 d0 general control bass control msb lsb level (db) 0 0 1 x 0 0 0 0 ? 12 0 0 1 x 0 0 0 1 ? 10 0 0 1 x 0 0 1 0 ? 8 0 0 1 x 0 0 1 1 ? 6 0 0 1 x 0 1 0 0 ? 4 0 0 1 x 0 1 0 1 ? 2 0 0 1 x 0 1 1 0 0 0 0 1 x 0 1 1 1 2 0 0 1 x 1 0 0 0 4 0 0 1 x 1 0 0 1 6 0 0 1 x 1 0 1 0 8 0 0 1 x 1 0 1 1 10 0 0 1 x 1 1 0 0 12 bass control power up state x 0 1 1 0 bass control is flat
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 13 rev.a, 12/29/2011 treble control msb lsb level (db) 0 1 0 x 0 0 0 0 ? 12 0 1 0 x 0 0 0 1 ? 10 0 1 0 x 0 0 1 0 ? 8 0 1 0 x 0 0 1 1 ? 6 0 1 0 x 0 1 0 0 ? 4 0 1 0 x 0 1 0 1 ? 2 0 1 0 x 0 1 1 0 0 0 1 0 x 0 1 1 1 2 0 1 0 x 1 0 0 0 4 0 1 0 x 1 0 0 1 6 0 1 0 x 1 0 1 0 8 0 1 0 x 1 0 1 1 10 0 1 0 x 1 1 0 0 12 treble control power up state x 0 1 1 0 treble control is flat general control msb lsb function 1 1 1 0 chip on 1 1 1 1 chip shutdown 1 1 1 0 speaker enable 1 1 1 1 speaker disable 1 1 1 0 stereo enhance off 1 1 1 1 stereo enhance on 1 1 1 0 mute disable 1 1 1 1 mute enable general control power up state 0 0 0 0 0
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 14 rev.a, 12/29/2011 application information layout as stated in the grounding section, placement of ground return lines is critical for maintaining the highest level of system performance. it is not only important to route the correct ground return lines together, but also important to be aware of where those ground return lines are routed in conjunction with each other. the output load ground returns should be physically located as far as reasonably possible from low signal level lines and their ground return lines. critical signal lines are those relating to the microphone amplifier section, since these lines generally work at very low signal levels. supply bypassing as with all op amps and power op amps, the IS31AP4832 requires the supplies to be bypassed to avoid oscillation. to avoid high frequency instabilities, a 0.1 f metallized-film or ceramic capacitor should be used to bypass the supplies as close to the chip as possible. for low frequency considerations, a 10 f or greater tantalum or electrolytic capacitor should be paralleled with the high frequency bypass capacitor. if power supply bypass capacitors are not sufficiently large, the current in the power supply leads, which is a rectified version of the output current, may be fed back into internal circuitry. this internal feedback signal can cause high frequency distortion and oscillation. if power supply lines to the chip are long, larger bypass capacitors could be required. long power supply leads have inductance and resistance associated with them that could prevent peak low frequency current demands from being met. the extra bypass capacitance will reduce the peak current requirements from the power supply lines. power-up status on power-up or after a hard reset, the IS31AP4832 registers will be initialized with the default values listed in the truth tables. by default, the tone controls are all flat, 3d enhance is off, and the chip is in stereo mode. click-and-pop circuitry the IS31AP4832 contains circuitry to minimize turn-on transients or ?click and pops?. in this case, turn-on refers to either power supply turn-on or the device coming out of shutdown mode. when the devices turn on, the amplifiers are internally configured as unity gain buffers. an internal current source charges the bypass capacitor on the bypass pin. both the inputs and outputs ideally track the voltage at the bypass pin. the device will remain in buffer mode until the bypass pin has reached its half supply voltage, 1/2v dd . as soon as the bypass node is stable, the device will become fully operational. although the bypass pin current source cannot be modified, the size of the bypass capacitor, cb, can be changed to alter the device turn-on time and the amount of ?click and pop?. by increasing cb, the amount of turn-on pop can be reduced. however, the trade-off for using a larger bypass capacitor is an increase in the turn-on time for the device. reducing cb will decrease turn-on time and increase ?click and pop?. there is a linear relationship between the size of cb and the turn-on time. some typical turn-on times for different values of cb are: c b t on 0.1 f 50ms 1 f 130ms in order to eliminate ?click and pop?, all capacitors must be discharged before turn-on. rapid on/off switching of the device or shutdown function may cause the ?click and pop? circuitry to not operate fully, resulting in increased ?click and pop? noise. coupling capacitors because the IS31AP4832 is a single supply circuit, all audio signals must be capacitor coupled to the chip to remove the 2.5 v dc bias. all audio inputs have 20k ? input impedances, so the ac-coupling capacitor will create a high-pass filter with f ? 3db = 1/(2 20k ? c in ) power amplifier the power amplifiers in the IS31AP4832 are designed to drive 8 ? or 32 ? loads at 1.2 w (continuous) and 90mw (continuous), respectively, with 1% thd+n. as shown in the typical performance characteristics, the power amplifiers typically drive 4 ? loads at 350mw, but with a slight increase in high-frequency thd. as discussed above, these outputs should be ac-coupled to the output load. bridge configuration explanation as shown in figure 1, the IS31AP4832 consists of two pairs of operational amplifiers, forming a two-channel (channel a and channel b) stereo amplifier. external feedback resistors rf and input resistors ri set the closed-loop gain of amp a (nouta) and amp b (nouta) whereas two internal 20k ? resistors set amp a?s (pouta) and amp b?s (pouta) gain at 1. the IS31AP4832 drives a load, such speaker, connected between the two amplifier outputs, nouta and pouta. figure 1 shows that amp a?s (nouta) output serves as amp a?s (pouta) input. this results in both amplifiers producing signals identical in magnitude, but 180 out of phase. taking advantage of this phase difference, a load is placed between nouta and
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 15 rev.a, 12/29/2011 pouta and driven differentially (commonly referred to as ?bridge mode?). this results in a differential gain of a vd = 2(rf/ri) (1) bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier?s output and ground. for a given supply voltage, bridge mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing across the load. this produces four times the output power when compared to a single-ended amplifier under the same conditions. this increase in attainable output power assumes that the amplifier is not current limited another advantage of the differential bridge output is no net dc voltage across the load. this is accomplished by biasing channel a?s and channel b?s outputs at half-supply. this eliminates the coupling capacitor that single supply, single ended amplifiers require. eliminating an output coupling capacitor in a single-ended configuration forces a single-supply amplifier?s half-supply bias voltage across the load. this increases internal ic power dissipation and may permanently damage loads such as speakers. i2c interface the IS31AP4832 uses a serial bus, which conforms to the i 2 c protocol, to control the chip?s functions with two wires: clock and data. the clock line is uni-directional. the data line is bi-directional (open-collector) with a pull-up resistor (typically 10k ? ).the maximum clock frequency specified by the i 2 c standard is 400khz. in this discussion, the master is the microcontroller and the slave is the IS31AP4832. the timing diagram for the i 2 c is shown in figure 22 . the data is latched in on the stable high level of the clock and the data line should be held high when not in use. the timing diagram is broken up into six major sections: the ?start? signal is generated by lowering the data signal while the clock signal is high. the start signal will alert all devices attached to the i 2 c bus to check the incoming address against their own chip address. the 8-bit chip address is sent next, most significant bit first. each address bit must be stable while the clock level is high. after the last bit of the address is sent, the master checks for the IS31AP4832?s acknowledge. the master releases the data line high (through a pull-up resistor). then the master sends a clock pulse. if the IS31AP4832 has received the address correctly, then it holds the data line low during the clock pulse. if the data line is not low, then the master should send a ?stop? signal (discussed later) and abort the transfer. the 8 bits of data are sent next, most significant bit first. each data bit should be valid while the clock level is stable high. after the data byte is sent, the master must generate another acknowledge seeing if the IS31AP4832 received the data. if the master has more data bytes to send to the IS31AP4832, then the master can repeat the previous two steps until all data bytes have been sent. the ?stop? signal ends the transfer. to signal ?stop?, the data signal goes high while the clock signal is high. 3d audio enhancement the IS31AP4832 has a 3d audio enhancement effect that helps improve the apparent stereo channel separation when, because of cabinet or equipment limitations, the left and right speakers are closer to each other than optimal. an external rc network is required to enable the effect. the amount of the effect is set by the 5k ? resistor. a 220nf capacitor is used to reduce the effect at frequencies below 140hz. increasing the value of the capacitor will decrease the low cutoff frequency at which the stereo enhanced effect starts to occur as shown below f (?3db) = 1/2 r 3d c 3d decreasing the resistor size will make the 3d effect more pronounced and decreasing the capacitor size will raise the cutoff frequency for the effect. tone control response bass and treble tone controls are included in the IS31AP4832. the tone controls use two external capacitors for each stereo channel. each has a corner frequency determined by the value of c1 (connected between loop out and tone in) and c2 (connected between tone out and loop in) and internal resistors in the feedback loop of the internal tone amplifier. typically, c1 = c2 and for 100 hz and 10khz corner frequencies, c1 = c2 = 2.2nf. altering the ratio between c1 and c2, changes the midrange gain. for example, if c1 = 2(c2), then the frequency response will be flat at 20hz and 20khz, but will have a 6db peak at 1khz. with c = c1 = c2, the treble turn-over frequency is nominally f tt = 1/(2 c(56k ? )) and the bass turn-over frequency is nominally f bt = 1/(2 c(113.3k ? )), when maximum boost is chosen. the inflection points (the frequencies where the boost or cut is within 3db of the final value) are, for treble and bass respectively, f ti = 1/(2 c(7.1k ? )) f bi = 1/(2 c(631.7k ? )) increasing the values of c1 and c2 decreases the
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 16 rev.a, 12/29/2011 turnover and inflection frequencies: i.e., the tone control response curves shown in typical performance section will shift left when c1 and c2 are increased and shift right when c1 and c2 are decreased. with c1 = c2 = 0.0022 f, 2db steps are achieved at 100hz and 10khz. changing c1 and c2 to 0.001 f shifts the 2db step frequency to 220hz and 25khz. if the tone control capacitors? size is decreased these frequencies will increase. with c1 = c2 = 0.0033 f the 2db steps take place at 68hz and 7.6khz.
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 17 rev.a, 12/29/2011 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. figure 23 classification profile
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 18 rev.a, 12/29/2011 tape and reel information
IS31AP4832 integrated silicon solution, inc. ? www.issi.com 19 rev.a, 12/29/2011 package information qfn-28 note: all dimensions in millimeters unless otherwise stated.

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